1. Field of the Invention
The present invention relates to a clamping circuit used for a correlation-double sampling (CDS) of a pixel signal output from a solid-state imaging apparatus.
2. Description of the Related Art
Various types of solid-state imaging apparatuses such as a CCD type apparatus, a CMOS type apparatus and the like have been proposed and put into practice. It is conventionally known that, in such apparatuses, the correlation double sampling (CDS) is extremely effective in suppressing noises of pixel signals including a black level and a signal level. In the correlation double sampling, the black level of each pixel signal is clamped at a clamping potential and then, during a signal level period, the clamping is released and a variation from the black level to the signal level is sampled and held.
For example, in the CCD type imaging apparatus, since a reset noise is generated for each pixel signal in correlation with the black level and the signal level, the reset noise can be removed by the above-described CDS operation. In the CMOS type imaging apparatus, since a fixed pattern noise is generated in correlation with the black level and the signal level, the fixed pattern noise can also be removed by the CDS operation. Furthermore, in any type of solid-state imaging apparatus, although a MOS type output amplifier is likely to generate a noise within a low frequency range, the low frequency noise can be suppressed by a CDS operation because there is a correlation between a black level and a signal level corresponding to each other.
In order to achieve this CDS operation, specialized elements other than the CCD are frequently used in the CCD type imaging apparatus. Therefore, the CCD type imaging apparatus results in a complicated circuit configuration in connection with a clamping circuit and a sample-hold circuit. For the CMOS type imaging apparatus, a relatively simple circuit configuration is proposed because the CCD and the CDS circuit can be easily integrated.
There is an example of the clamping circuit using a clamping capacitance and an inverting amplifier, which is described in Japanese Laid-Open Publication No. 5-207220. This publication discloses a technology for reducing a variation of each inverting amplifier by using a plurality of inverting amplifiers. However this technique does not directly relate to the present invention; therefore, a description thereof is omitted, except specific features of the clamping circuit shown in FIGS. 6A to 6C. FIG. 6A is a block diagram showing the entirety of a clamping circuit. FIG. 6B is a circuit diagram showing an inverting amplifier in the clamping circuit. FIG. 6C is a graph for illustrating an operation of the inverting amplifier.
As shown in FIG. 6B, an inverting amplifier 102 includes a combination of n-type MOSFETs 111 and 112. In the inverting amplifier 102, where threshold values of FETs 111 and 112 are VT1, and VT2, respectively, the following expressions (1) are satisfied:
Vo greater than Vixe2x88x92VT1, VDxe2x88x92Vo greater than VDxe2x88x92Voxe2x88x92VT2xe2x80x83xe2x80x83(1)
where Vi represents an input voltage (a pixel signal from a solid-state imaging apparatus), Vo represents an output voltage of a clamping circuit 101, and VD represents a power source voltage.
Under the conditions defined by the expressions (1), FETs 111 and 112 operate in a saturation region. In this case, currents ID flowing in the FETs 111 and 112 are equal, so that the following expression (2) is satisfied:
Kxc3x97(W1/L1)xc3x97(Vi+VT1)2=Kxc3x97(W2/L2)xc3x97(VDxe2x88x92Voxe2x88x92VT2)2xe2x80x83xe2x80x83(2)
where K represents a transconductance parameter, W1 and W2 represent channel widths of the FETs 111 and 112, respectively, and L1 and L2 represent channel lengths of the FETs 111 and 112, respectively.
Furthermore, from the expression (2), the output voltage Vo of the clamping circuit 101 is represented by the following expression (3):
Vo=xe2x88x92xcex1xc3x97(Vi+VT1)+(VDxe2x88x92VT2)xe2x80x83xe2x80x83(3)
where xcex1={square root over ( )}((W1/L1)/(W2/L2)).
The graph of FIG. 6C shows the relationship of the input voltage Vi and the output voltage Vo. In the graph of FIG. 6C, a linear portion 121 satisfies the expression (3).
In the clamping circuit shown in FIG. 6A, Vi=Vo=V1 in the state that an input and an output of the inverting amplifier 102 are short-circuited.
When the FETs 111 and 112 are of an enhancement type, VT1 greater than 0, VT2 greater than 0. Therefore, when a clamping switch SW1 is turned OFF to separate the input and the output from each other, Vi less than V1, Vo greater than V1, which satisfy the expression (1). Thus, the FETs 111 and 112 operate in a saturation region, i.e., in the linear portion 121 of FIG. 6C. Accordingly, a ratio of an output variation vo to an input variation vi is represented by the following expression (4):
vo/vi=xe2x88x92xcex1xe2x80x83xe2x80x83(4)
Under the above conditions, in the clamping circuit shown in FIG. 6A, when the clamping switch SW1 is turned ON by a control signal xcfx86c to short-circuit the input and the output of the inverting amplifier 102, a clamping potential becomes V1. Thereafter, when the clamping switch SW1 is turned OFF and the input signal Vi is input while maintaining the OFF-state, a DC component of the input signal Vi is cut off by a clamping capacitance Cc. In addition, an AC component of the input signal Vi, i.e., the variation vi, is amplified by the inverting amplifier 102 with a gain of xe2x88x92xcex1, and the variation vo is output from the inverting amplifier 102. At this time, an output side potential of the inverting amplifier 102 is vo+V1. Since a value xcex1 can be set at any large value as can be easily seen from the expression (3), the amplification can be carried out. Furthermore, the voltage V1, which is to be a clamping voltage, is always fixed at any point in the linear portion 121 of FIG. 6C as described above by the input-output short circuiting, whereby an optimum operation point is obtained.
Assuming that the clamping circuit shown in FIG. 6A is operated at a high speed at the same periodic cycle as that of a pixel signal, each of the signals in the clamping circuit varies as shown in, for example, FIG. 7.
FIG. 7 shows the input voltage Vin (a pixel signal from the solid-state imaging apparatus). Within period T3 of the pixel signal, period T1 is a black level period, and period T2 is a signal level period.
As shown in FIG. 7, even when the variation vi of a signal level with respect to the black level is constant in each pixel signal, the signal level varies for each pixel signal on a pixel signal-by-pixel signal basis due to a noise inherent in the solid-state imaging apparatus.
Such a noise inherent in the solid-state imaging apparatus is suppressed by the clamping operation. As shown in FIG. 7, during period T4 within period T1, the clamping switch SW1 is turned ON by the control signal xcfx86c to short-circuit the input and the output of the inverting amplifier 102. The black level is then clamped at a clamping potential V1. Thereafter, the clamping is released, so that only the variation vi of the signal level is input to the inverting amplifier 102 through a clamping capacitance Cc. As a result, the variation vo (AC component) amplified with a gain of xe2x88x92xcex1 by the inverting amplifier 102 is provided as shown in FIG. 7. This suppresses the noise component of the pixel signal, so that only the signal level of the pixel signal is accurately extracted.
However, in the above conventional clamping circuit, the clamping potential includes:
1) a kTC noise introduced into the input side of the inverting amplifier 102 when the switch SW1 is turned ON; and
2) a noise generated at the output side of the inverting amplifier made of MOSFETs.
The kTC noise 1), which is generated even in an ideal case where the inverting amplifier includes no noise, is represented by the following expression (5):
VnA={square root over ( )}(kT/C)xe2x80x83xe2x80x83(5)
where C represents an effective capacity at the input side of the inverting amplifier, k represents the Boltzmann constant, and T represents the absolute temperature.
The noise 2) is generally represented by the following expression (6):
xe2x80x83VnB={square root over ( )}(xcex12xc3x97(Vn1)2+(Vn2)2)xe2x80x83xe2x80x83(6)
where Vn1 represents an equivalent noise which occurs at the FET 111 side (FIG. 6B), and Vn2 represents an equivalent noise which occurs at the FET 112 side. Each of Vn1 and Vn2 represents a sum of a thermal noise and a flicker noise.
Therefore, the sum of the noises VnA and VnB, shown in the following expression (7), appears at the clamping potential:
Vn={square root over ( )}((VnA)2+(VnB)2)xe2x80x83xe2x80x83(7)
Thus, the noise of the clamping potential includes the kTC noise, the thermal noise, and the flicker noise. The kTC noise and the thermal noise are white noises, and the flicker noise appears at a periodic cycle of 1/f (f represents frequency).
However, since the pixel signal is sampled by the clamping operation at a cycle of period T3=1/fc, a noise spectrum of the clamping potential is limited by the Nyquist threshold, fN=fc/2, resulting in a characteristic curve VN shown in FIG. 8. Likewise, a spectrum of the pixel signal is limited by the Nyquist threshold, fN=fc/2, due to the sampling, resulting in a characteristic curve Vs shown in FIG. 8.
In view of the above discussions, the clamping potential is not stable at a value of V1 shown in FIG. 6C, and varies due to a noise of the characteristic curve VN in FIG. 8 included in the noise Vn represented by the expression (7). For example, as shown in FIG. 7, when the clamping potential varies with respect to the voltage V1 by the amount of a noise component xcex94vo because of a noise component xcex94vn, the signal level varies by the amount of a noise component xcex94vo. This deteriorates the picture quality.
In other words, in the above described conventional circuit, a noise having a correlation with the black level and the signal level can be removed. However, when the clamping potential varies due to the noise Vn, the variation influences the signal level and therefore the picture quality deteriorates.
With reference to FIG. 6A, where Z represents an output impedance of the inverting amplifier 102 and Cxe2x80x2 represents a parasitic capacitance of the input side of the inverting amplifier 102, the time constant, xcfx84=Cxe2x80x2xc3x97Z, should be sufficiently shorter than ON period T4 of the control signal xcfx86c. In this case, an operation frequency band of the inverting amplifier 102 is higher than the Nyquist threshold, fN=fc/2. Thus, the operation frequency band does not affect signal processings at a frequency band fN or less.
According to one aspect of the present invention, a clamping circuit of a solid-state imaging apparatus for receiving a pixel signal including a black level and a signal level through a signal line and outputting the pixel signal with noise being suppressed, the clamping circuit includes: a first capacitance and an inverting amplifier inserted into the signal line and connected to each other in series; a first switch and a second switch connected to each other in series to form a serial circuit; and a second capacitance connected between the first and second switches of the serial circuit and a constant potential, wherein both sides of the serial circuit including the first switch and the second switch are connected to an input side and an output side of the inverting amplifier, respectively; the first switch and the second switch are opened and closed in synchronization with a clock signal; and a time constant defined by an output-side impedance of the inverting amplifier and the second capacitance when the first switch and the second switch are closed is sufficiently greater than a cycle of the clock signal.
In another embodiment of the present invention, the first switch includes a first MOSFET of a first conductive type and a second MOSFET of a second conductive type which are connected in parallel with each other; the second switch includes a third MOSFET of the first conductive type and a fourth MOSFET of the second conductive type which are connected in parallel with each other; the first MOSFET and the third MOSFET are driven by a first control signal; the second MOSFET and the fourth MOSFET are driven by a second control signal; and a polarity of the first control signal and a polarity of the second control signal are different from each other.
In still another embodiment of the present invention, a clamping circuit of a solid-state imaging apparatus further includes a sample-hold circuit for sampling and holding a signal level of the pixel signal input from the inverting amplifier, in which: in a black level period of the pixel signal, the first switch and the second switch are closed to perform a clamping operation, and in a signal level period of the pixel signal, the sample-hold circuit samples and holds a signal level of the pixel signal.
In still another embodiment of the present invention, the second capacitor is an external capacitor.
Hereinafter, the function of the present invention will be described.
According to the present invention, when first and second switches are turned ON during the clamping operation, a sufficiently large second capacitance is connected between a signal line and a constant potential (e.g., a ground potential). Thus, a noise component of the clamping potential on the signal line is cut off through the second capacitance, thereby reducing the amount of noises in the circuitry.
According to one embodiment of the invention, the first and second switches are made of a first conductive type MOSFET and a second conductive type MOSFET (e.g., n-type and p-type), and these transistors are driven by control signals which are opposite in phase to each other. Thus, an inductive noise generated due to the switch operation is canceled, whereby the clamping operation can be performed while achieving further noise reduction.
According to one embodiment of the invention, a sample-hold circuit is connected to the clamping circuit at a subsequent stage thereto. In such a configuration, a sample-hold operation is performed during a signal level period of a pixel signal from the solid-state imaging apparatus, while a clamping operation is performed during a black level period of the pixel signal. In this manner, the correlation double sampling is conducted. When the correlation double sampling is combined with a low noise clamping operation, an ideal clamping and sampling with a low noise can be achieved.
According to one embodiment of the invention, since the second capacitance is provided by an external capacitor, it is easy to set the second capacitance at a sufficiently large value. Thus, a noise suppression effect by the low-pass filter can be further improved.
Thus, the invention described herein makes possible the advantage of providing a clamping circuit for a solid-state imaging apparatus which significantly suppresses a noise caused by a clamping operation with a simple circuit configuration so as to provide high quality images.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.